Code tracking loop with automatic power normalization

ABSTRACT

The present invention is for a receiver incorporated into User Equipment (UE) or base stations of a code division multiple access (CDMA) communication system. The UE and base station are in communication with one of the plurality of base stations and receives a communication signal through the receiver. The communication signal is correlated using a delay locked code tracking loop, that estimates and tracks a channel delay. The tracking loop comprises a reference code generator and an interpolator for generating timed signal versions in response to said communication. A timed signal correlator, included in the tracking loop for correlating at least two of the timed signal versions with the code reference signal. The result of the correlation is used for generating an error signal. An automatic power normalization loop (APN), that is responsive to the interpolator, generates a power error signal that normalizes the error signal through a normalization circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

The application is a continuation of U.S. patent application Ser. No.11/338,226, filed Jan. 24, 2006, now U.S. Pat. No. 7,529,292, issuingMay 5, 2009, which is a continuation of U.S. patent application Ser.No.10/686,057, filed Oct. 14, 2003, which is a continuation of U.S.patent application Ser. No. 10/252,640, filed Sep. 23, 2002, which is acontinuation of U.S. patent application Ser. No.10/034,867, filed Dec.27, 2001, now U.S. Pat. No. 6,456,648, issued Sep. 24, 2002, whichclaims priority from U.S. Provisional Patent Application No. 60/326,308,filed Oct. 1, 2001.

BACKGROUND

The present invention relates to a code tracking system for a receiverof a code division multiple access (CDMA) communication system. Morespecifically, the present invention relates to a second order codetracking system for more effectively removing the timing differencebetween the transmitted code and the received code.

Synchronization is an important task in any kind of telecommunication.There are several levels of synchronization, such as, carrier,frequency, code, symbol, frame and network synchronization. In all theselevels, synchronization can be distinguished into two phases, which areacquisition (initial synchronization) and tracking (finesynchronization).

A typical wireless communication system sends downlink communicationsfrom a base station to one or a plurality of User Equipments (UEs) anduplink communications from UEs to the base station. A receiver withinthe UE works by correlating, or despreading, the received downlinksignal with a known code sequence. The sequence must be exactlysynchronized to the received sequence in order to get the maximal outputfrom the correlator. The receiver should be able to easily adapt to achange in the environment of a radio line changing without ceasingoperation. In order to accomplish this, present receivers gather as muchof the transmitted signal energy as possible in order to maximize thesignal-to-noise ratio. In multi-path fading channels, however, thesignal energy is dispersed over a certain amount of time due to distinctecho paths and scattering. One crucial task of the receiver is thus toestimate the channel to improve its performance. If the receiver hasinformation about the channel profile, one way of gathering signalenergy is then to assign several correlator branches to different echopaths and combine their outputs constructively, a structure known as theRAKE receiver.

The RAKE receiver has several fingers, one for each echo path, and ineach finger, the path delay with respect to some reference delay such asa direct or the earliest received path, must be estimated and trackedthroughout the transmission. The estimation of the paths initialposition in time is obtained by using a multi-path search algorithm. Themulti-path search algorithm does an extensive search through correlatorsto locate the paths with a chip accuracy. After these initial positionsare found, the tracking units generate accurate estimates for the delaysof several multi-path components by means of early-late timing errordetectors and utilize these estimates for the different delays to shiftthe phase of the codes. This type of tracking unit is known as anearly-late gate synchronizer. A delay-locked loop (DLL) is commonly usedto implement the early-late gate synchronizer. Illustrated in FIG. 1 isa block diagram of this delay-locked loop. The bandwidth of the CodeTracking Loop (CTL) determines the noise filtering capability of thesynchronizer. The narrower the bandwidth, the more robust thesynchronizer is to distortion from noise and less sensitive to smallsignal changes. The bandwidth of the loop depends on the parameters ofthe loop filter (alpha, beta), total loop gain (K_(T)), and input signalpower level (P_(in)). Damping ratio of the loop also depends on the sameparameters. Damping ratio of the loop determines the stability of theloop. Although the parameters of the loop can be fixed, it is verydifficult to fix the input signal level.

Most of the digital receivers employ some form of Automatic Gain Control(AGC) in their physical layers. Although AGC limits the input signallevel, the dynamic level of the signal level is still large. This is dueto the fact that AGC is actually designed to prevent the Analog toDigital Converter (ADC) from entering saturation.

Since the dynamic range of the input signal level is not effectivelylimited, the bandwidth and damping ratio of the code tracking loopchanges with input signal power. This results in degradation inperformance for the code tracking loop.

Accordingly, there exists a need for a code tracking loop that maintainsthe bandwidth and damping ratio of the loop regardless of changes withthe input signal power level.

Other objects and advantages of the present invention will becomeapparent after reading the description of the preferred embodiment.

SUMMARY

The present invention is a receiver, included in a user equipment (UE),of a code division multiple access (CDMA) communication system whichincludes the UE and a plurality of base stations. The UE is incommunication with one of the plurality of base stations and receives acommunication signal from the base station through the receiver. Thecommunication signal is correlated by said receiver using a delay lockedcode tracking loop, that estimates and tracks a channel delay of thecommunication signal. The tracking loop comprises a reference codegenerator for generating a reference code signal and an interpolator forgenerating timed signal versions in response to the receipt of saidcommunication. A timed signal correlator, also included in the trackloop for correlating at least two of the timed signal versions with thecode reference signal. The result of the correlation is used forgenerating an error signal. An automatic power normalization loop (APN),which is responsive to the interpolator, generates a power error signalthat is used to normalize the error signal through a normalizationcircuit.

BRIEF DESCRIPTION OF THE DRAWING(S)

FIG. 1 is a block diagram of a prior art delay-locked tracking loop.

FIG. 2 is a block diagram of a delay-locked code tracking loop withautomatic power normalization in accordance with the present invention.

FIG. 3 is a flow diagram of the delay-locked code tracking loop of thepresent invention.

FIG. 4 is a block diagram of an exemplary loop filter included in thedelay-locked tracking loop of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

The preferred embodiment will be described with reference to the drawingfigures wherein like numerals repeat like elements throughout.

Illustrated in FIG. 2 is a block diagram of the delay-locked codetracking loop (DCTL) 10 in accordance with the preferred embodiment ofthe present invention. The DCTL comprises an interpolator 11, twointegrate and dump devices 12 a, 12 b, two squaring devices 13 a, 13 b,a normalization device 14, a loop filter 15, a code generator 16, anaccumulator 17, a limiter 18, a quantizer 19, a gain circuit 9, and anautomatic power normalization loop (APN) 20. The delay-lock codetracking loop 10 receives an input signal x (t−T), where T is the timingerror in the received signal. Since the timing error is confined to −Tcto Tc, where Tc is the chip duration using the multi-path searchalgorithm, the only way to shift the incoming signal is by usingmathematical interpolation. Accordingly, the interpolator 11, coupled tothe integrate devices 12 a, 12 b, the code generator 16, and the APN 20,receives the input signal x (t−T) and creates three outputs: Punctual,Early and Late. As those skilled in the art know, the Early and Lateoutputs are a half chip early and a half chip late versions of thepunctual output, respectively. They are all obtained by interpolation ofthe incoming signal x (t−T). After the interpolator 11, down-samplingtakes place, all three outputs are preferably down-sampled by anover-sampling ratio of the transmitted signal. The punctual output isthe main output of the DCTL 10, the early and late outputs are used onlyinside the code tracking loop 10 algorithm.

The early and late signals are correlated with the output of thereference code generator 16, such as a pilot code generator, in lowerand upper branches of the DCTL using the integrate devices 12 a, 12 b,respectively. Once the outputs of the code generator 16 and the earlyand late outputs have been correlated, the correlated signals areforwarded to squaring devices 13 a, 13 b, respectively. Since phasesynchronization is not acquired at this stage, squaring is used toobtain non-coherent CTL.

After correlation and squaring, the difference of the two branches(early and late) are taken to produce an error signal e(t), which isproportional to the timing error. The error signal e(t) is then powernormalized against a power error signal (P_(e)) by the normalizationcircuit 14 (to be disclosed hereinafter) and output to the loop filter15.

The loop filter 15, coupled to the normalization device 14 and theaccumulator 17, filters the normalized error signal e(t) and forwards itto the accumulator 17. An exemplary loop filter is a classicalproportional integrator (PI) filter, but any first order low-pass filterwould be appropriate for the present invention. The PI filter, includinga loop filter accumulator 41, has two branches, as shown in FIG. 4. Onebranch creates a control signal proportional to the current value of theerror signal and the other branch produces a signal proportional to theaverage value of the error signal. These signals are combined afterbeing multiplied by two different constants, alpha and beta. Theaccumulator 41 inside the PI filter works exactly the same way as theaccumulator 17 described below.

The accumulator 17, coupled to the loop filter and a gain circuit 9,receives the filtered error signal from the loop filter 15 and processesthe signal. Those having skills in the art know that the accumulator 17simply adds its current input to its previous output. Initially, theoutput of the accumulator 17 is set to zero. There is an overflowdetection inside the accumulator to limit the output value. Theaccumulation by the accumulator 17 together with the loop filter 15 isused to obtain the second order feedback loop response. The accumulator17 then forwards the error signal e(t) to the gain circuit 9.

The gain circuit 9, coupled to the accumulator 17 and a limiter circuit18, receives the output of the accumulator 17 and adjust the level ofthe filtered signal to match the interpolator 11 timing shift value.This circuit changes the sign in the timing air signal to correct thetiming delay/advance of the incoming signal reference to the codegenerator 16. Once this is accomplished, the gain circuit 9 forwards theadjusted error signal e(t) to a limiter circuit 18 that limits the overshoot of the error signal if it is above the chip duration −Tc to Tc.The limiter 18 forwards the error signal to the quantizer 19 where thediscrete value of the delay estimate is obtained and forwarded back tothe interpolator 11. In this design, a thirty-two (32) level quantizeris used to obtain an accuracy of Tc/16. Although any level of quantizercan be used for different levels of delay estimate accuracy

DCTL is a second order feedback loop. In control system notation, thesystem function, H(s), for a second order feedback loop can be writtenas:

$\begin{matrix}{{{H(s)} = \frac{{2{\zeta\omega}_{n}s} + \omega_{n}^{2}}{s^{2} + {2{\zeta\omega}_{n}s} + \omega_{n}^{2}}},} & {{Equation}\mspace{14mu} (1)}\end{matrix}$

where ζ is the damping ratio and ω_(n) is the natural frequency of thesystem. These can be written in terms of the parameters of the DCTL asfollows:

$\begin{matrix}{{\omega_{n} = \sqrt{2\sqrt{P_{in}}K_{T}\beta}},} & {{Equation}\mspace{14mu} (2)} \\{{\zeta = \frac{K_{T}\alpha \sqrt{P_{in}}}{\omega_{n}}},} & {{Equation}\mspace{14mu} (3)}\end{matrix}$

where alpha and beta are the loop filter parameters, K_(T)=K_(S)K is thetotal open loop gain including the S-curve gain and the external gain,and P_(in) is the input signal power. The two-sided noise bandwidth ofthe system is given by

$\begin{matrix}{W_{L} = {{\omega_{n}( {\zeta + \frac{1}{4\; \zeta}} )}.}} & {{Equation}\mspace{14mu} (4)}\end{matrix}$

As an example, a Universal Mobile Telecommunications System (UMTS)Frequency Division Duplex (FDD) UE receiver design with a chip rate of3.84 MHz and 2 times over-sampling use the following values: spreadingfactor of 256 for the pilot code, loop gain K=0.01, alpha=0.0141, andbeta=0.00001. The values of natural frequency and damping ratiodetermine the main characteristics of the loop such as stability, gainand phase margins, bandwidth, convergence time, and steady state jitter.These characteristics are fixed during the design and should not changewith respect to the input. Otherwise, the DCTL may malfunction andproduce unexpected results. However, as seen from equations 2, 3, and 4,they all depend on input signal power, P_(in), which may changeconsiderably during the communication process.

In order to overcome the effects of the input signal x (t−T) power levelchanging, an Automatic Power Normalization loop 20 (APN) is included inthe delay-locked tracking loop 10 of the present invention. The APN 20,coupled to the interpolator 11, the code generator 16 and thenormalization circuit 11, comprises an integrate and dump circuit 21, asquaring device 22, an adder 24, and a moving average (MA) filter 23.The punctual output from the interpolator 11 is the input to the APNloop 20. The punctual signal is received by the integrate and dumpcircuit 21 along with the signal from the code generator 16. Theintegrate and dump circuit 21 is coupled to the code generator 16, theinterpolator 11, and the squaring device 22. Similar to the integrateand dump circuits 12 a, 12 b disclosed above, the integrate and dumpcircuit 21 correlates the punctual signal received from the interpolator11 with the signal received from the reference code generator 16. Oncethe two signals are correlated the integrate circuit 21 forwards thecorrelated signal to the squaring device 22.

The squaring device 22, coupled to the integrate circuit 21 and theadder 24, squares the correlated signal and forwards the squared signalto the adder 24. The adder 24 subtracts the squared output from thesquaring device 22 from a reference signal power (P) the referencesignal power (P) is a predetermined value and is used in the design ofthe DLL 10 to set the parameters. As those skilled in the art know, thereference power level (P) may be any predetermined value. Thesubtracting of the squared signal by the adder 24 results in a powerdifference signal, which is forwarded to the moving average filter 23.

The Moving Average (MA) filter 23, coupled to the adder 24 and thenormalization circuit 14, receives the difference signal and filters it.The MA filter 23 consists of a real valued register of size N, an adder,and a constant multiplier with a factor of 1/N. Each time a new input ispassed to the MA filter 23 the register elements are shifted one to theright. The element that came the earliest (on the right most side) iscleared and the current input value is placed in the left most place inthe register. After this shift, each element in the register is added.The total value is multiplied by 1/N to produce the average value forthe power error signal (Pe). It is preferable that N be selected to betwenty (20), which corresponds to 20 symbols processed. The MA filtersize is selected such that it will be insensitive to instantaneous powerchanges due to fading, however it will compensate for the average inputsignal level changes. Once the MA filter 23 filters the power differencesignal, a filtered power error signal P_(e) is forwarded to thenormalization circuit 14.

The normalization circuit 14, coupled to the squaring devices 13 a, 13 band the APN 20, receives the error e(t) corresponding to the differencebetween the late and early outputs of the interpolator 11 and the powererror signal P_(e) from the APN 20. In order to normalize the errorsignal e(t) against the power error signal P_(e), the normalizationcircuit 14 multiplies the error signal e(t) by (P/(P+P_(e))), where P isthe referenced signal power level used in the APN loop 20.

The normalization of the error signal instead of the input signalresults in a reduced number of multiplications (normalization) by afactor equal to the spreading factor. Preferably, integrated into thenormalization circuit there is a limiter (not shown) that limits themultiplication factor from 0.1 to 10 or −20 dB to 20 dB. This limiter isused to prevent noise amplification.

The flow diagram of the delay-lock code tracking loop in accordance withthe preferred embodiment of the present invention is illustrated in FIG.3. An input signal in received by the DLL circuit 10 (step 301). Theinterpolator 11 of the DLL circuit 10 produces the late, early andpunctual outputs (step 302). The late and early outputs are correlatedwith the code generator 16 (step 303 a), and the difference between thecorrelated signals is determined, producing an error signal e(t) (step304 a). Simultaneous to the late and early outputs, the punctual outputis correlated with the code generator (step 303 b) and subtracted from apredetermined reference power level to produce a power level differencesignal (step 304 b). The power level difference signal is then filteredto produce a power level error signal Pe (step 305 b). The error signalcorresponding to the late and early outputs, is normalized against thepower level error signal Pe from the APN loop 20 (step 306). Thenormalized error signal is then processed to produce a delay estimate(step 307) which is forwarded back to the input of the DLL tracking loop10 (step 308).

While the present invention has been described in terms of the preferredembodiment, other variations which are within the scope of the inventionas outlined in the claims below will be apparent to those skilled in theart.

1. A base station comprising: a receiver for receiving a communicationsignal; and a delay locked code tracking loop (DCTL) configured toestimate and track a channel delay of the received communication signal,the DCTL comprising: a reference code generator configured to generate areference code signal; an interpolator configured to generate a baseversion of the received communication signal and a plurality of timeoffset versions thereof; a timed signal correlator configured tocorrelate each of the time offset signal versions with the codereference signal and combining the correlations for generating an errorsignal; an automatic power normalization loop (APN) configured togenerate a power error signal based on the base signal version and thereference code signal; and a normalization circuit configured tonormalize the error signal using the power error signal to generate anormalized error signal used for controlling the generation of the basesignal version by the interpolator.
 2. The base station of claim 1wherein the APN includes: an APN correlator configured to correlate thebase signal version and the reference code signal to generate acorrelated signal; an adder configured to subtract the correlated signalfrom a power reference signal, producing a power difference signal; anda filter, responsive to the adder, configured to filter the powerdifference to generate the power error signal.
 3. The base station ofclaim 2 wherein the DCTL further comprises: a loop filter, coupled tothe normalization circuit, configured to filter the normalized errorsignal; an accumulator, responsive to the loop filter, configured tochange the error signal; a gain circuit, coupled to the accumulator,configured to change the sign in the error signal to correct a timingdelay/advance of the received communication signal to the reference codesignal; and a quantizer configured to generate a discrete value of thedelay/advance for controlling the generating of the base signal versionby the interpolator.
 4. The base station of claim 2 wherein the timeoffset versions are an early version and a later version of the baseversion.
 5. The base station of claim 4 wherein the early version is ahalf chip early and the late version is a half chip late of the baseversion.
 6. A method for estimating and tracking a channel delay of areceived communication comprising: generating a reference code signal;interpolating the received communication signal to generate a baseversion of the communication signal and a plurality of time offsetversions thereof; correlating each of the time offset signal versionwith the code reference signal and combining the correlations togenerate an error signal; generating a power error signal based on thebase signal version and the reference code signal; and normalizing theerror signal using the power error signal to generate a normalized errorsignal used for controlling the generation of the base signal version.7. The method of claim 6 wherein generating a power error signalincludes: correlating the base signal version and the reference codesignal to generate a correlated signal; subtracting the correlatedsignal from a power reference signal, producing a power differencesignal; and filtering the power difference to generate the power errorsignal.
 8. The method of claim 7 further comprising: filtering thenormalized error signal; accumulating the error signal; changing thesign in the error signal to correct a timing delay/advance of thereceived communication to the reference code signal; and generating adiscrete value of the delay/advance for controlling the generation ofthe base signal version.
 9. The method of claim 6 wherein the timeoffset versions are an early version and a late version of the baseversion.
 10. The method of claim 9 wherein the early version is a halfchip early and the late version is a half chip late of the base version.